Apparatuses and methods for write address tracking

ABSTRACT

Apparatuses and methods are provided for write address tracking. An example apparatus can include an array of memory cells and a cache coupled to the array. The example apparatus can include tracking circuitry coupled to the cache. The tracking circuitry can be configured to track write addresses of data written to the cache.

PRIORITY INFORMATION

This application is a Continuation of U.S. application Ser. No.15/215,296, filed Jul. 20, 2016, which issues as U.S. Pat. No.10,733,089 on Aug. 4, 2020, the contents of which are incorporatedherein by reference.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory andmethods, and more particularly, to apparatuses and methods for writeaddress tracking.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuits in computers or other computing systems. There aremany different types of memory including volatile and non-volatilememory. Volatile memory can require power to maintain its data (e.g.,host data, error data, etc.) and includes random access memory (RAM),dynamic random access memory (DRAM), static random access memory (SRAM),synchronous dynamic random access memory (SDRAM), and thyristor randomaccess memory (TRAM), among others. Non-volatile memory can providepersistent data by retaining stored data when not powered and caninclude NAND flash memory, NOR flash memory, and resistance variablememory such as phase change random access memory (PCRAM), resistiverandom access memory (RRAM), and magnetoresistive random access memory(MRAM), such as spin torque transfer random access memory (STT RAM),among others.

Computing systems often include a number of processing resources (e.g.,one or more processors), which may retrieve and execute instructions andstore the results of the executed instructions to a suitable location. Aprocessing resource (e.g., CPU) can comprise a number of functionalunits such as arithmetic logic unit (ALU) circuitry, floating point unit(FPU) circuitry, and/or a combinatorial logic block, for example, whichcan be used to execute instructions by performing logical operationssuch as AND, OR, NOT, NAND, NOR, and XOR, and invert (e.g., inversion)logical operations on data (e.g., one or more operands). For example,functional unit circuitry may be used to perform arithmetic operationssuch as addition, subtraction, multiplication, and/or division onoperands via a number of logical operations.

A number of components in a computing system may be involved inproviding instructions to the functional unit circuitry for execution.The instructions may be executed, for instance, by a processing resourcesuch as a controller and/or host processor. Data (e.g., the operands onwhich the instructions will be executed) may be stored in a memory arraythat is accessible by the functional unit circuitry. The instructionsand/or data may be retrieved from the memory array and sequenced and/orbuffered before the functional unit circuitry begins to executeinstructions on the data. Furthermore, as different types of operationsmay be executed in one or multiple clock cycles through the functionalunit circuitry, intermediate results of the instructions and/or data mayalso be sequenced and/or buffered. Data stored in the memory arrayand/or intermediate results of the instructions may be stored in amemory cache. The memory cache can be used to transfer and/or operate onthe stored data. When data located in the cache is operated on, changed,and/or updated, the data may conflict with corresponding data stored inthe memory array. In order to update the memory array, an entire cacheof data may be written to the memory array in order to correlate thedata in the cache to the data in the memory array.

In many instances, the processing resources (e.g., processor and/orassociated functional unit circuitry) may be external to the memoryarray, and data is accessed via a bus between the processing resourcesand the memory array to execute a set of instructions. Processingperformance may be improved in a processor-in-memory (PIM) device, inwhich a processor may be implemented internal and/or near to a memory(e.g., directly on a same chip as the memory array). A PIM device maysave time by reducing and/or eliminating external communications and mayalso conserve power.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an apparatus in the form of a computingsystem including one example of a processing in memory (PIM) capabledevice coupled to a host in accordance with the present disclosure.

FIG. 2 is a schematic diagram illustrating a system for tracking writeaddresses in accordance with the present disclosure.

FIG. 3 is a block diagram illustrating a portion of one example of a PIMcapable device in greater detail in accordance with the presentdisclosure.

FIG. 4 is a schematic diagram illustrating sensing circuitry of a memorydevice in accordance with a number of embodiments of the presentdisclosure.

FIG. 5 is a schematic diagram illustrating circuitry for data transferin a memory device in accordance with a number of embodiments of thepresent disclosure.

DETAILED DESCRIPTION

An example apparatus includes an array of memory cells and a cachecoupled to the array. The example apparatus can include trackingcircuitry coupled to the cache. The tracking circuitry can be configuredto track write addresses of data written to the cache.

According to various embodiments of the present disclosure, trackingcircuitry is configured to track write addresses. For example, data canbe written from a memory array to a cache. At least a portion of thedata written to the cache can be updated and the data in the cache canbe written to the memory array to maintain consistency between thememory array and the cache. Further, a write address associated with thedata can be tracked when the write address corresponds to data in acache that has been updated. For example, when data in a cacheassociated with a first write address is updated to include a change inthat data in the cache, the first write address is tracked as beingupdated (e.g., a latch corresponding to the first write address may setan indicator bit). In addition, when data in a cache associated with asecond write address is not updated, the second write address isindicated as not being updated (e.g., a latch corresponding to thesecond write address may not have one or more indicator bits set). Inprevious approaches, in response to a command to transfer data from acache to a memory array the entire cache may be written to the memoryarray to maintain consistency of data between them. However, this caninvolve significant power and/or transfer time to write data (includingnon-updated data) from the cache to the memory array. Thus, in someembodiments where data in the memory array is written into the cache butnot updated, duplicative power and/or additional transfer time may beinvolved as data that is already consistent will be transferred (e.g.,the non-updated data will be written even though the non-updated datahas not changed).

In accordance with embodiments of the present disclosure, data may bewritten to a cache. The data written to the cache can be updated andwritten back to the memory array. In response to a command to write thedata in the cache to the memory array, the data that has been updatedand is associated with the first write address can be written to thememory array and data that has not been updated and is associated withthe second write address will not be written to the memory array. Inthis way, power and/or transfer time will be saved by transferringupdated data from the cache to the memory array without transferringdata that has not been updated.

In the following detailed description of the present disclosure,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration how one or more embodimentsof the disclosure may be practiced. These embodiments are described insufficient detail to enable those of ordinary skill in the art topractice the embodiments of this disclosure, and it is to be understoodthat other embodiments may be utilized and that process, electrical,and/or structural changes may be made without departing from the scopeof the present disclosure. As used herein, “a number of” a particularthing can refer to one or more of such things (e.g., a number of memoryarrays can refer to one or more memory arrays). A “plurality of” isintended to refer to more than one of such things.

The figures herein follow a numbering convention in which the firstdigit or digits correspond to the drawing figure number and theremaining digits identify an element or component in the drawing.Similar elements or components between different figures may beidentified by the use of similar digits. For example, 130 may referenceelement “30” in FIG. 1, and a similar element may be referenced as 230in FIG. 2. As will be appreciated, elements shown in the variousembodiments herein can be added, exchanged, and/or eliminated so as toprovide a number of additional embodiments of the present disclosure. Inaddition, as will be appreciated, the proportion and the relative scaleof the elements provided in the figures are intended to illustratecertain embodiments of the present invention, and should not be taken ina limiting sense.

FIG. 1 is a block diagram of an apparatus in the form of a computingsystem 100 including one example of a processing in memory (PIM) capabledevice 101 coupled to a host 110. The PIM capable device 101 (alsoreferred to as “memory device 101”) may include a controller 140. FIG. 1is provided as an example of a system including a current PIM capabledevice 101 architecture.

As shown in the example of FIG. 1, the memory device 101 may include amemory array 130, a command interface 136, sensing circuitry 150, andadditional logic circuitry 170. The system 100 can include separateintegrated circuits or both the logic and memory can be on the sameintegrated device as with a system on a chip (SoC). The system 100 canbe, for instance, a server system and/or a high performance computing(HPC) system and/or a portion thereof.

For clarity, the system 100 has been simplified to focus on featureswith relevance to the present disclosure. The memory array 130 can be aDRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAMarray, NAND flash array, and/or NOR flash array, for instance. The array130 can comprise memory cells arranged in rows coupled by access lines(which may be referred to herein as word lines or select lines) andcolumns coupled by sense lines, which may be referred to herein as datalines or digit lines. Although a single array 130 is shown in FIG. 1,embodiments are not so limited. For instance, memory device 101 mayinclude a number of arrays 130 (e.g., a number of banks of DRAM cells,NAND flash cells, etc.).

The memory device 101 includes address circuitry 142 to latch addresssignals provided over a data bus 156 (e.g., an I/O bus) through I/Ocircuitry 144. Status and/or exception information can be provided fromthe controller 140 on the memory device 101 to a host 102 and/or logicresource through an out-of-band bus 157. Address signals are receivedthrough address circuitry 142 and decoded by a row decoder 146 and acolumn decoder 152 to access the memory array 130. Data can be read frommemory array 130 by sensing voltage and/or current changes on the datalines using sensing circuitry 150. The sensing circuitry 150 can readand latch a page (e.g., row) of data from the memory array 130. The I/Ocircuitry 144 can be used for bi-directional data communication withhost 110 over the data bus 156. The write circuitry 148 is used to writedata to the memory array 130. Address, control and/or commands, e.g.,processing in memory (PIM) commands, may be received to the controller140 via bus 154.

Command interface 136 may include control registers, e.g., double datarate (DDR) control registers in a DRAM, to control the operation of thearray 130, e.g., DRAM array, and/or controller 140. As such, the commandinterface 136 may be coupled to the I/O circuitry 144 and/or controller140. In various embodiments the command interface 136 may be memorymapped I/O registers. The memory mapped I/O registers can be mapped to aplurality of locations in memory where microcode instructions arestored. However, embodiments are not so limited. For example, any numberof memory arrays with a cache between the main array and a hostinterface can use the command interface 136.

In various embodiments, controller 140 may decode signals received viabus 154 from the host 110. These signals can include chip enablesignals, write enable signals, and address latch signals that are usedto control operations performed on the memory array 130, including dataread, data write, and data erase operations. In one or more embodiments,portions of the controller 140 can be a reduced instruction set computer(RISC) type controller operating on 32 and/or 64 bit lengthinstructions. In various embodiments, the controller 140 is responsiblefor executing instructions from the host 110 and/or logic components inassociation with the sensing circuitry 150 to perform logical Booleanoperations such as AND, OR, XOR, etc. Further, the controller 140 cancontrol shifting data (e.g., right or left) in an array, e.g., memoryarray 130. Additionally, portions of the controller 140 can includecontrol logic, a sequencer, timing circuitry and/or some other type ofcontroller, described further in connection with FIG. 2.

Examples of the sensing circuitry 150 and its operations are describedfurther below in connection with FIG. 4. In various embodiments thesensing circuitry 150 can comprise a plurality of sense amplifiers and aplurality of compute components, which may serve as and be referred toherein as an accumulator, and can be used to perform logical operations(e.g., on data associated with complementary data lines).

In various embodiments, the sensing circuitry 150 can be used to performlogical operations using data stored in array 130 as inputs and storethe results of the logical operations back to the array 130 withouttransferring data via a sense line address access (e.g., without firinga column decode signal). As such, various compute functions can beperformed using, and within, sensing circuitry 150 rather than (or inassociation with) being performed by processing resources external tothe sensing circuitry (e.g., by a processing resource associated withhost 110 and/or other processing circuitry, such as ALU circuitry,located on memory device 101 (e.g., on controller 140 or elsewhere)).

In various previous approaches, data associated with an operand, forinstance, would be read from memory via sensing circuitry and providedto external ALU circuitry via I/O lines (e.g., via local I/O linesand/or global I/O lines). The external ALU circuitry could include anumber of registers and would perform compute functions using theoperands, and the result would be transferred back to the array via theI/O lines. In contrast, in a number of embodiments of the presentdisclosure, sensing circuitry 150 is configured to perform logicaloperations on data stored in memory array 130 and store the result backto the memory array 130 without enabling an I/O line (e.g., a local I/Oline) coupled to the sensing circuitry 150. The sensing circuitry 150can be formed on pitch with the memory cells of the array 130.Additional peripheral sense amplifiers, extended row address (XRA)registers, cache and/or data buffering, e.g., additional logic circuitry170, can be coupled to the sensing circuitry 150 and can be used tostore, e.g., cache and/or buffer, results of operations describedherein.

Thus, in various embodiments, circuitry external to array 130 andsensing circuitry 150 is not needed to perform compute functions as thesensing circuitry 150 can perform the appropriate logical operations toperform such compute functions without the use of an external processingresource. Therefore, the sensing circuitry 150 may be used to complimentand/or to replace, at least to some extent, such an external processingresource (or at least the bandwidth consumption of such an externalprocessing resource).

However, in a number of embodiments, the sensing circuitry 150 may beused to perform logical operations (e.g., to execute instructions) inaddition to logical operations performed by an external processingresource (e.g., on host 110). For instance, processing resources on host110 and/or sensing circuitry 150 on memory device 101 may be limited toperforming only certain logical operations and/or a certain number oflogical operations.

Enabling an I/O line can include enabling (e.g., turning on) atransistor having a gate coupled to a decode signal (e.g., a columndecode signal) and a source/drain coupled to the I/O line. However,embodiments are not limited to not enabling an I/O line. For instance,in a number of embodiments, the sensing circuitry (e.g., 150) can beused to perform logical operations without enabling column decode linesof the array; however, the local I/O line(s) may be enabled in order totransfer a result to a suitable location other than back to the array130 (e.g., to an external register).

FIG. 2 is a schematic diagram illustrating a system for tracking writeaddresses in accordance with the present disclosure. The systemillustrated in FIG. 2 can include a memory array 230 coupled to a cache270. The memory array 230 can store data to be processed by thecontroller 240 and/or additional controllers (not illustrated). The datastored in the memory array 230 can be stored to the cache 270 in anumber of memory cells and/or registers. The data stored to the cache270 can be requested by additional components and/or memory locations(such as memory bank 321-7 in FIG. 3). For example, a memory location(e.g., memory bank 321-7) may request data stored in the memory array230 that is also stored in the cache 270 for processing. The data can betransferred from the cache 270 to the memory location using a number ofI/O lines (e.g., shared I/O line 555 in FIG. 5).

A controller 240 can be coupled to the cache 270. The controller 240 cansend a number of indications to the cache 270. A first indication 274can indicate to copy data in the cache 270 to the memory array 230. Asecond indication 276 can indicate column addresses 276 associated withdata to the cache 270, indicating where the data is stored in the cache270 and/or in the memory array 230.

A command interface 236 can be coupled to the cache 270. The commandinterface 236 can be a Double Data Rate (DDR) Synchronous DynamicRandom-Access Memory (SDRAM) command interface. The command interface236 can send a write command 266 to the cache 270. The write command 266can be transferred through latch circuitry 260 of the cache 270 andindicate to the latch circuitry that data 272 associated with the writecommand 266 will be updated. While the tracking circuitry includinglogic 264 and latch circuitry 260 is illustrated as being a portion ofthe cache 270, embodiments are not so limited. For example, the logic264 and/or the latch circuitry 260 can be located outside the cache 270and can be coupled to and/or in communication with the cache 270.

The latch circuitry 260 can include a latch 262 that corresponds to aparticular write address. For example, the command interface 236 cansend a write command 266 to write a particular portion of data 272associated with a particular column address 268. In response to thewrite command 266 being sent to the latch circuitry 260, the latch 262can store a particular data value. The latch 262 storing the particulardata value can be a set flag that indicates that the portion of data 272(corresponding to the column address 268) has been updated.

As described herein, in response to a controller sending an indication274 to copy data in the cache 270 to the memory array 230, portions ofthe data of the cache 270 that include a set flag in the latch circuitry260 are written to the memory array. For example, data (e.g., data 272)associated with a latch (e.g., latch 262) that stores a data valueindicating the data has been updated and/or written to is written to thememory array 230. Additional portions of the data of the cache 270 thatdo not include a set flag (e.g., a latch corresponding to each columnaddress of the additional portions includes a data value that indicatesthe additional portions have not been updated) are not written to thememory array 230. For example, a column address 276 associated with datato be written from the cache 270 to the memory array 230 can becompared, using logic circuitry 264, to a column address 268 associatedwith data indicated by the command interface 236 to be updated in thecache.

Put another way, the command interface can send write commands 266 tothe cache to update a first set of data 272 associated with columnaddresses 268. In response to the controller 240 indicating, at 274, towrite data from the cache 270 associated with indicated columnaddresses, at 276, to the memory array 230, the first set of data 272 iswritten to the memory array 230 and a second set of data (notillustrated) is not written to the memory array 230. For example, thecontroller indicates, at 274, to copy a first set of column addresses(indicated at 276). The first set of column addresses are received bylogic circuitry 264 and compared to the column addresses 268 that haveentered the latch circuitry 260. In response to a column address at 274matching a column address 268 that includes a set flag in acorresponding latch 262, the data associated with set flag is written tothe memory array. Each of the column addresses indicated at 276 arecompared to a corresponding latch 262 and written to the memory array230 when a corresponding latch 262 includes a set flag and not writtento the memory array 230 when the corresponding latch 262 does notinclude a set flag. This can avoid having to transfer a full cache tothe memory array 230 in response to at least a portion of the data inthe cache being updated and/or altered.

In some embodiments, the controller 240 can indicate to copy columnaddresses 276 associated with all data stored in the cache 270. Thelatch circuitry 260 can track column addresses that correspond toupdated data 272. The unwritten and/or non-updated column addresses canbe masked such that in response to all column addresses of the cache 270being selected to be written to the memory array 230, only the columnaddresses of data that have been updated are written to the memory array230. Masking can include blocking column select activation lines of theunwritten data of the column addresses and/or disabling write datadrivers associated with the unwritten data of the column addresses. Forexample, array write paths (from the cache 270 to the memory array 230)are enabled for addresses associated with data written (updated) to thecache 270. Array write paths (from the cache 270 to the memory array230) are masked for addresses associated with data not written(non-updated) to the cache 270. The write address latch circuitry 260can be cleared in response to a write from the cache 270 to the memoryarray 230. In this way, transferring of updated data is not duplicatedand tracking of write addresses is restarted after each write to thememory array 230 from the cache 270.

In some embodiments, a number of I/O data lines can determine aconfiguration of the system. For example, a system with 64 I/O lines canuse a minimum data size of 512 bits such that eight cycles can becorrelated to a 4 k data transfer at a time. In this example, 32 enablebits would be used to store data in a 16 k wide data register. Further,32 enable bits each corresponding to 512 bits equals 16 k wide data. Inan example including a system with 32 I/O lines, a minimum data size of256 bits can be used with 64 enable bits for a 16 k wide data register.In an example including a system with 16 I/O lines, a minimum data sizeof 128 bits can be used with 128 enable bits for a 16 k wide dataregister.

In a number of embodiments, a cache control mode can be used to controlreads and writes. For example, a particular word line and a particularcolumn address of the cache 270 can be activated such that an entirecache 270 of data is not transferred.

FIG. 3 is another block diagram in greater detail of a portion of oneexample of a PIM capable device 320 such as memory device 101 in FIG. 1.In the example of FIG. 3, a controller 340-1, . . . , 340-7 (referred togenerally as controller 340) may be associated with each bank 321-1, . .. , 321-7 (referred to generally as 321) to the PIM capable device 320.Eight banks are shown in the example of FIG. 3. However, embodiments arenot limited to this example number. Controller 340 may representcontroller 140 shown in FIG. 1. Each bank may include one or more arraysof memory cells (not shown). For example each bank may include one ormore arrays such as array 130 in FIG. 1 and can include decoders, othercircuitry and registers shown in FIG. 1. In the example PIM capabledevice 320 shown in FIG. 3, controllers 340-1, . . . , 340-7 are shownhaving control logic 331-1, . . . , 331-7, sequencers 332-1, . . . ,332-7, and timing circuitry 333-1, . . . , 333-7 as part of a controller340 on one or more memory banks 321 of a memory device 320. The PIMcapable device 320 may represent part of memory device 101 shown in FIG.1.

As shown in the example of FIG. 3, the PIM capable device 320 mayinclude a high speed interface (HSI) 341 to receive data, addresses,control signals, and/or commands at the PIM capable device 320. Invarious embodiments, the HSI 341 may be coupled to a bank arbiter 345associated with the PIM capable device 320. The HSI 341 may beconfigured to receive commands and/or data from a host, e.g., 110 as inFIG. 1. As shown in the example of FIG. 3, the bank arbiter 345 may becoupled to the plurality of banks 321-1, . . . , 321-7.

In the example shown in FIG. 3, the control logic 331-1, . . . , 331-7may be in the form of a microcoded engine responsible for fetching andexecuting machine instructions, e.g., microcode instructions, from anarray of memory cells, e.g., an array as array 130 in FIG. 1, that ispart of each bank 321-1, . . . , 321-7 (not detailed in FIG. 3). Thesequencers 332-1, . . . , 332-7 may also be in the form of microcodedengines. Alternatively, the control logic 331-1, . . . , 331-7 may be inthe form of a very large instruction word (VLIW) type processingresource and the sequencers 332-1, . . . , 332-7, and the timingcircuitry 333-1, . . . , 333-7 may be in the form of state machines andtransistor circuitry.

The control logic 331-1, . . . , 331-7 may decode microcode instructionsinto function calls, e.g., microcode function calls (uCODE), implementedby the sequencers 332-1, . . . , 332-7. The microcode function calls canbe the operations that the sequencers 332-1, . . . , 332-7 receive andexecute to cause the PIM device 320 to perform particular logicaloperations using the sensing circuitry such as sensing circuitry 150 inFIG. 1. The timing circuitry 333-1, . . . , 333-7 may provide timing tocoordinate performance of the logical operations and be responsible forproviding conflict free access to the arrays such as array 130 in FIG.1.

As described in connection with FIG. 1, the controllers 340-1, . . . ,340-7 may be coupled to sensing circuitry 150 and/or additional logiccircuitry 170, including cache, buffers, sense amplifiers, extended rowaddress (XRA) latches, and/or registers 350/370-1, associated witharrays of memory cells via control lines and data paths shown in FIG. 3as 355-1, 355-7. As such, sensing circuitry 150 and logic 170 shown inFIG. 1 can be associated to the arrays of memory cells 130 using dataI/Os shown as 355-1, . . . , 355-7 in FIG. 3. The controllers 340-1, . .. , 340-7 may control regular DRAM operations for the arrays such as aread, write, copy, and/or erase operations, etc. Additionally, however,microcode instructions retrieved and executed by the control logic331-1, . . . , 331-7 and the microcode function calls received andexecuted by the sequencers 332-1, . . . , 332-7 cause sensing circuitry150 shown in FIG. 1 to perform additional logical operations such asaddition, multiplication, or, as a more specific example, Booleanoperations such as an AND, OR, XOR, etc., which are more complex thanregular DRAM read and write operations. Hence, in this PIM capabledevice 320 example, microcode instruction execution and logic operationsare performed on the banks 321-1, . . . , 321-7 to the PIM device 320.

As such, the control logic 331-1, . . . , 331-7, sequencers 332-1, . . ., 332-7, and timing circuitry 333-1, . . . , 333-7 may operate togenerate sequences of operation cycles for a DRAM array. In the PIMcapable device 320 example, each sequence may be designed to performoperations, such as a Boolean logic operations AND, OR, XOR, etc., whichtogether achieve a specific function. For example, the sequences ofoperations may repetitively perform a logical operation for a one (1)bit add in order to calculate a multiple bit sum. Each sequence ofoperations may be fed into a first in/first out (FIFO) buffer coupled tothe timing circuitry 333-1, . . . , 333-7 to provide timing coordinationwith the sensing circuitry 150 and/or additional logic circuitry 170associated with the array of memory cells 130, e.g., DRAM arrays, shownin FIG. 1.

In the example PIM capable device 320 shown in FIG. 3, the timingcircuitry 333-1, . . . , 333-7 provides timing and provides conflictfree access to the arrays from four (4) FIFO queues. In this example,one FIFO queue may support array computation, one may be for Instructionfetch, one for microcode (e.g., Ucode) instruction fetch, and one forDRAM I/O. Both the control logic 331-1, . . . , 331-7 and the sequencers332-1, . . . , 332-7 can generate status information, which is routedback to the bank arbiter 345 via a FIFO interface. The bank arbiter 345may aggregate this status data and report it back to a host 110 via theHSI 341.

FIG. 4 is a schematic diagram illustrating sensing circuitry 450 inaccordance with a number of embodiments of the present disclosure. Thesensing circuitry 450 can correspond to sensing circuitry 150 shown inFIG. 1.

A memory cell can include a storage element (e.g., capacitor) and anaccess device (e.g., transistor). For instance, a first memory cell caninclude transistor 402-1 and capacitor 403-1, and a second memory cellcan include transistor 402-2 and capacitor 403-2, etc. In thisembodiment, the memory array 430 is a DRAM array of 1T1C (one transistorone capacitor) memory cells, although other embodiments ofconfigurations can be used (e.g., 2T2C with two transistors and twocapacitors per memory cell). In a number of embodiments, the memorycells may be destructive read memory cells (e.g., reading the datastored in the cell destroys the data such that the data originallystored in the cell is refreshed after being read).

The cells of the memory array 430 can be arranged in rows coupled byaccess (word) lines 404-X (Row X), 404-Y (Row Y), etc., and columnscoupled by pairs of complementary sense lines (e.g., digit linesDIGIT(D) and DIGIT(D)_ shown in FIG. 4 and DIGIT_0 and DIGIT_0* shown inFIG. 5). The individual sense lines corresponding to each pair ofcomplementary sense lines can also be referred to as digit lines 405-1for DIGIT (D) and 405-2 for DIGIT (D)_, respectively, or correspondingreference numbers in FIG. 5. Although only one pair of complementarydigit lines are shown in FIG. 4, embodiments of the present disclosureare not so limited, and an array of memory cells can include additionalcolumns of memory cells and digit lines (e.g., 4,096, 8,192, 16,384,etc.).

Although rows and columns are illustrated as orthogonally oriented in aplane, embodiments are not so limited. For example, the rows and columnsmay be oriented relative to each other in any feasible three-dimensionalconfiguration. For example, the rows and columns may be oriented at anyangle relative to each other, may be oriented in a substantiallyhorizontal plane or a substantially vertical plane, and/or may beoriented in a folded topology, among other possible three-dimensionalconfigurations.

Memory cells can be coupled to different digit lines and word lines. Forexample, a first source/drain region of a transistor 402-1 can becoupled to digit line 405-1 (D), a second source/drain region oftransistor 402-1 can be coupled to capacitor 403-1, and a gate of atransistor 402-1 can be coupled to word line 404-Y. A first source/drainregion of a transistor 402-2 can be coupled to digit line 405-2 (D)_, asecond source/drain region of transistor 402-2 can be coupled tocapacitor 403-2, and a gate of a transistor 402-2 can be coupled to wordline 404-X. A cell plate, as shown in FIG. 4, can be coupled to each ofcapacitors 403-1 and 403-2. The cell plate can be a common node to whicha reference voltage (e.g., ground) can be applied in various memoryarray configurations.

The memory array 430 is configured to couple to sensing circuitry 450 inaccordance with a number of embodiments of the present disclosure. Inthis embodiment, the sensing circuitry 450 comprises a sense amplifier406 and a compute component 431 corresponding to respective columns ofmemory cells (e.g., coupled to respective pairs of complementary digitlines). The sense amplifier 406 can be coupled to the pair ofcomplementary digit lines 405-1 and 405-2. The compute component 431 canbe coupled to the sense amplifier 406 via pass gates 407-1 and 407-2.The gates of the pass gates 407-1 and 407-2 can be coupled to operationselection logic 413.

The operation selection logic 413 can be configured to include pass gatelogic for controlling pass gates that couple the pair of complementarydigit lines un-transposed between the sense amplifier 406 and thecompute component 431 and swap gate logic for controlling swap gatesthat couple the pair of complementary digit lines transposed between thesense amplifier 406 and the compute component 431. The operationselection logic 413 can also be coupled to the pair of complementarydigit lines 405-1 and 405-2. The operation selection logic 413 can beconfigured to control continuity of pass gates 407-1 and 407-2 based ona selected operation.

The sense amplifier 406 can be operated to determine a data value (e.g.,logic state) stored in a selected memory cell. The sense amplifier 406can comprise a cross coupled latch, which can be referred to herein as aprimary latch. In the example illustrated in FIG. 4, the circuitrycorresponding to sense amplifier 406 comprises a latch 415 includingfour transistors coupled to a pair of complementary digit lines D 405-1and (D)_ 405-2. However, embodiments are not limited to this example.The latch 415 can be a cross coupled latch (e.g., gates of a pair oftransistors) such as n-channel transistors (e.g., NMOS transistors)427-1 and 427-2 are cross coupled with the gates of another pair oftransistors, such as p-channel transistors (e.g., PMOS transistors)429-1 and 429-2).

In operation, when a memory cell is being sensed (e.g., read), thevoltage on one of the digit lines 405-1 (D) or 405-2 (D)_ will beslightly greater than the voltage on the other one of digit lines 405-1(D) or 405-2 (D)_. An ACT signal and an RNL* signal can be driven low toenable (e.g., fire) the sense amplifier 406. The digit lines 405-1 (D)or 405-2 (D)_ having the lower voltage will turn on one of the PMOStransistor 429-1 or 429-2 to a greater extent than the other of PMOStransistor 429-1 or 429-2, thereby driving high the digit line 405-1 (D)or 405-2 (D)_ having the higher voltage to a greater extent than theother digit line 405-1 (D) or 405-2 (D)_ is driven high.

Similarly, the digit line 405-1 (D) or 405-2 (D)_ having the highervoltage will turn on one of the NMOS transistor 427-1 or 427-2 to agreater extent than the other of the NMOS transistor 427-1 or 427-2,thereby driving low the digit line 405-1 (D) or 405-2 (D)_ having thelower voltage to a greater extent than the other digit line 405-1 (D) or405-2 (D)_ is driven low. As a result, after a short delay, the digitline 405-1 (D) or 405-2 (D)_ having the slightly greater voltage isdriven to the voltage of the supply voltage V_(CC) through a sourcetransistor, and the other digit line 405-1 (D) or 405-2 (D)_ is drivento the voltage of the reference voltage (e.g., ground) through a sinktransistor. Therefore, the cross coupled NMOS transistors 427-1 and427-2 and PMOS transistors 429-1 and 429-2 serve as a sense amplifierpair, which amplify the differential voltage on the digit lines 405-1(D) and 405-2 (D)_ and operate to latch a data value sensed from theselected memory cell.

Embodiments are not limited to the sense amplifier 406 configurationillustrated in FIG. 4. As an example, the sense amplifier 406 can be acurrent-mode sense amplifier and a single-ended sense amplifier (e.g.,sense amplifier coupled to one digit line). Also, embodiments of thepresent disclosure are not limited to a folded digit line architecturesuch as that shown in FIG. 4.

The sense amplifier 406 can, in conjunction with the compute component431, be operated to perform various operations using data from an arrayas input. In a number of embodiments, the result of an operation can bestored back to the array without transferring the data via a digit lineaddress access and/or moved between banks without using an external databus (e.g., without firing a column decode signal such that data istransferred to circuitry external from the array and sensing circuitryvia local I/O lines). As such, a number of embodiments of the presentdisclosure can enable performing operations and compute functionsassociated therewith using less power than various previous approaches.Additionally, since a number of embodiments eliminate the need totransfer data across local and global I/O lines and/or external databuses in order to perform compute functions (e.g., between memory anddiscrete processor), a number of embodiments can enable an increased(e.g., faster) processing capability as compared to previous approaches.

The sense amplifier 406 can further include equilibration circuitry 414,which can be configured to equilibrate the digit lines 405-1 (D) and405-2 (D)_. In this example, the equilibration circuitry 414 comprises atransistor 424 coupled between digit lines 405-1 (D) and 405-2 (D)_. Theequilibration circuitry 414 also comprises transistors 425-1 and 425-2each having a first source/drain region coupled to an equilibrationvoltage (e.g., V_(DD)/2), where V_(DD) is a supply voltage associatedwith the array. A second source/drain region of transistor 425-1 can becoupled digit line 405-1 (D), and a second source/drain region oftransistor 425-2 can be coupled digit line 405-2 (D)_. Gates oftransistors 424, 425-1, and 425-2 can be coupled together, and to anequilibration (EQ) control signal line 426. As such, activating EQenables the transistors 424, 425-1, and 425-2, which effectively shortsdigit lines 405-1 (D) and 405-2 (D)_ together and to the equilibrationvoltage (e.g., V_(DD)/2).

Although FIG. 4 shows sense amplifier 406 comprising the equilibrationcircuitry 414, embodiments are not so limited, and the equilibrationcircuitry 414 may be implemented discretely from the sense amplifier406, implemented in a different configuration than that shown in FIG. 4,or not implemented at all.

As described further below, in a number of embodiments, the sensingcircuitry 450 (e.g., sense amplifier 406 and compute component 431) canbe operated to perform a selected operation and initially store theresult in one of the sense amplifier 406 or the compute component 431without transferring data from the sensing circuitry via a local orglobal I/O line and/or moved between banks without using an externaldata bus (e.g., without performing a sense line address access viaactivation of a column decode signal, for instance).

Performance of operations (e.g., Boolean logical operations involvingdata values) is fundamental and commonly used. Boolean logicaloperations are used in many higher level operations. Consequently, speedand/or power efficiencies that can be realized with improved operations,can translate into speed and/or power efficiencies of higher orderfunctionalities.

As shown in FIG. 4, the compute component 431 can also comprise a latch,which can be referred to herein as a secondary latch 464. The secondarylatch 464 can be configured and operated in a manner similar to thatdescribed above with respect to the primary latch 415, with theexception that the pair of cross coupled p-channel transistors (e.g.,PMOS transistors) included in the secondary latch can have theirrespective sources coupled to a supply voltage (e.g., V_(DD)), and thepair of cross coupled n-channel transistors (e.g., NMOS transistors) ofthe secondary latch can have their respective sources selectivelycoupled to a reference voltage (e.g., ground), such that the secondarylatch is continuously enabled. The configuration of the computecomponent 431 is not limited to that shown in FIG. 4, and various otherembodiments are feasible.

As described herein, a memory device (e.g., 101 in FIG. 1) can beconfigured to couple to a host (e.g., 110) via a data bus (e.g., 156)and a control bus (e.g., 154). A bank (e.g., bank 321-1 in FIG. 3) inthe memory device can include a plurality of subarrays of memory cells.The bank can include sensing circuitry (e.g., 150 in FIG. 1 andcorresponding reference numbers 450 in FIGS. 4 and 550 in FIG. 5)coupled to the plurality of subarrays via a plurality of columns (e.g.,522 in FIG. 5) of the memory cells. The sensing circuitry can include asense amplifier and a compute component (e.g., 406 and 431,respectively, in FIG. 4) coupled to each of the columns.

The bank can include a plurality of sensing stripes (e.g., 350/370 inFIG. 3) each with sensing circuitry coupled to a respective subarray ofthe plurality of the subarrays. A controller (e.g., 140 in FIG. 1)coupled to the bank can be configured to direct, as described herein,movement of data values stored in a first subarray (e.g., from datavalues in a row of the subarray sensed (cached) by the coupled sensingstripe) to be stored in latches of a latch stripe and/or a latchcomponent. Moving (e.g., copying, transferring, and/or transporting)data values between sense amplifiers and/or compute components (e.g.,406 and 431, respectively, in FIG. 4) in a sensing stripe andcorresponding sense amplifiers and/or compute components that formlatches in a latch stripe can be enabled by a number of selectablycoupled shared I/O lines (e.g., 355 in FIG. 3) shared by the sensingcomponent stripe and the latch stripe, as described herein.

The memory device can include a sensing stripe configured to include anumber of a plurality of sense amplifiers and compute components (e.g.,506-0, 506-1, . . . , 506-7 and 531-0, 531-1, . . . , 331-7,respectively, as shown in FIG. 5) that can correspond to a number of theplurality of columns (e.g., 522 in FIGS. 5 and 405-1 and 405-2 in FIG.4) of the memory cells, where the number of sense amplifiers and/orcompute components can be selectably coupled to the plurality of sharedI/O lines (e.g., via column select circuitry 558-1 and 558-2). Thecolumn select circuitry can be configured to selectably sense data in aparticular column of memory cells of a subarray by being selectablycoupled to a plurality of (e.g., four, eight, and sixteen, among otherpossibilities) sense amplifiers and/or compute components.

In some embodiments, a number of a plurality of sensing stripes (e.g.,350/370 in FIG. 3) in the bank can correspond to a number of theplurality of subarrays in the bank. A sensing stripe can include anumber of sense amplifiers and/or compute components configured to move(e.g., copy, transfer, and/or transport) an amount of data sensed from arow of the first subarray in parallel to a plurality of shared I/Olines. In some embodiments, the amount of data can correspond to atleast a thousand bit width of the plurality of shared I/O lines.

As described herein, the array of memory cells can include animplementation of DRAM memory cells where the controller is configured,in response to a command, to move (e.g., copy, transfer, and/ortransport) data from the source location to the destination location viaa shared I/O line. In various embodiments, the source location can be ina first bank and the destination location can be in a second bank in thememory device and/or the source location can be in a first subarray ofone bank in the memory device and the destination location can be in asecond subarray of a different bank. According to embodiments, the datacan be moved as described in connection with FIG. 1. The first subarrayand the second subarray can be in the same section of the bank or thesubarrays can be in different sections of the bank.

As described herein, the apparatus can be configured to move (e.g.,copy, transfer, and/or transport) data from a source location, includinga particular row (e.g., 519 in FIG. 5) and column address associatedwith a first number of sense amplifiers and compute components) to ashared I/O line. In addition, the apparatus can be configured to movethe data to a destination location, including a particular row andcolumn address associated with a second number of sense amplifiers andcompute components. As the reader will appreciate, each shared I/O line(e.g., 555) can actually include a complementary pair of shared I/Olines (e.g., shared I/O line and shared I/O line* as shown in theexample configuration of FIG. 4). In some embodiments described herein,2048 shared I/O lines (e.g., complementary pairs of shared I/O lines)can be configured as a 2048 bit wide shared I/O line.

FIG. 5 is a schematic diagram illustrating circuitry for data transferin a memory device in accordance with a number of embodiments of thepresent disclosure. FIG. 5 shows eight sense amplifiers (e.g., senseamplifiers 0, 1, . . . , 7 shown at 506-0, 506-1, . . . , 506-7,respectively) each coupled to a respective pair of complementary senselines (e.g., digit lines 505-1 and 505-2). FIG. 5 also shows eightcompute components (e.g., compute components 0, 1, . . . , 7 shown at531-0, 531-1, . . . , 531-7) each coupled to a respective senseamplifier (e.g., as shown for sense amplifier 0 at 506-0) via respectivepass gates 507-1 and 507-2 and digit lines 505-1 and 505-2. For example,the pass gates can be connected as shown in FIG. 4 and can be controlledby an operation selection signal, Pass. For example, an output of theselection logic can be coupled to the gates of the pass gates 507-1 and507-2 and digit lines 505-1 and 505-2. Corresponding pairs of the senseamplifiers and compute components can contribute to formation of thesensing circuitry indicated at 550-0, 550-1, . . . , 550-7.

Data values present on the pair of complementary digit lines 505-1 and505-2 can be loaded into the compute component 531-0 as described inconnection with FIG. 4. For example, when the pass gates 507-1 and 507-2are enabled, data values on the pair of complementary digit lines 505-1and 505-2 can be passed from the sense amplifiers to the computecomponent (e.g., 506-0 to 531-0). The data values on the pair ofcomplementary digit lines 505-1 and 505-2 can be the data value storedin the sense amplifier 506-0 when the sense amplifier is fired.

The sense amplifiers 506-0, 506-1, . . . , 506-7 in FIG. 5 can eachcorrespond to sense amplifier 406 shown in FIG. 4. The computecomponents 531-0, 531-1, . . . , 531-7 shown in FIG. 5 can eachcorrespond to compute component 431 shown in FIG. 4. A combination ofone sense amplifier with one compute component can contribute to thesensing circuitry (e.g., 550-0, 550-1, . . . , 550-7) of a portion of aDRAM memory subarray 525 configured to an I/O line 555 shared by anumber of sensing component stripes for subarrays and/or latchcomponents, as described herein. The paired combinations of the senseamplifiers 506-0, 506-1, . . . , 506-7 and the compute components 531-0,531-1, . . . , 531-7, shown in FIG. 5, can be included in the sensingstripes, as shown at 350/370-1 in FIG. 3.

The configurations of embodiments illustrated in FIG. 5 are shown forpurposes of clarity and are not limited to these configurations. Forinstance, the configuration illustrated in FIG. 5 for the senseamplifiers 506-0, 506-1, . . . , 506-7 in combination with the computecomponents 531-0, 531-1, . . . , 531-7 and the shared I/O line 555 isnot limited to half the combination of the sense amplifiers 506-0,506-1, . . . , 506-7 with the compute components 531-0, 531-1, . . . ,531-7 of the sensing circuitry being formed above the columns 522 ofmemory cells (not shown) and half being formed below the columns 522 ofmemory cells. Nor are the number of such combinations of the senseamplifiers with the compute components forming the sensing circuitryconfigured to couple to a shared I/O line limited to eight. In addition,the configuration of the shared I/O line 555 is not limited to beingsplit into two for separately coupling each of the two sets ofcomplementary digit lines 505-1 and 505-2, nor is the positioning of theshared I/O line 555 limited to being in the middle of the combination ofthe sense amplifiers and the compute components forming the sensingcircuitry (e.g., rather than being at either end of the combination ofthe sense amplifiers and the compute components).

The circuitry illustrated in FIG. 5 also shows column select circuitry558-1 and 558-2 that is configured to implement data movement operationswith respect to particular columns 522 of a subarray 525, thecomplementary digit lines 505-1 and 505-2 associated therewith, and theshared I/O line 555 (e.g., as directed by the controller 140 shown inFIG. 1). For example, column select circuitry 558-1 has select lines 0,2, 4, and 6 that are configured to couple with corresponding columns,such as column 0 (532-0), column 2, column 4, and column 6. Columnselect circuitry 558-2 has select lines 1, 3, 5, and 7 that areconfigured to couple with corresponding columns, such as column 1,column 3, column 5, and column 7.

Controller 140 can be coupled to column select circuitry 558 to controlselect lines (e.g., select line 0) to access data values stored in thesense amplifiers, compute components, and/or present on the pair ofcomplementary digit lines (e.g., 505-1 and 505-2 when selectiontransistors 559-1 and 559-2 are activated via signals from select line0). Activating the selection transistors 559-1 and 559-2 (e.g., asdirected by the controller 140) enables coupling of sense amplifier506-0, compute component 531-0, and/or complementary digit lines 505-1and 505-2 of column 0 (522-0) to move data values on digit line 0 anddigit line 0* to shared I/O line 555. For example, the moved data valuesmay be data values from a particular row 519 stored (cached) in senseamplifier 506-0 and/or compute component 531-0. Data values from each ofcolumns 0 through 7 can similarly be selected by controller 140activating the appropriate selection transistors.

Moreover, enabling (e.g., activating) the selection transistors (e.g.,selection transistors 559-1 and 559-2) can enable a particular senseamplifier and/or compute component (e.g., 506-0 and/or 531-0,respectively) to be coupled with a shared I/O line 555 such that datavalues stored by an amplifier and/or compute component can be moved to(e.g., placed on and/or transferred to) the shared I/O line 555. In someembodiments, one column at a time is selected (e.g., column 522-0) to becoupled to a particular shared I/O line 555 to move (e.g., copy,transfer, and/or transport) the stored data values. In the exampleconfiguration of FIG. 5, the shared I/O line 355 is illustrated as ashared, differential I/O line pair (e.g., shared I/O line and shared I/Oline*). Hence, selection of column 0 (522-0) could yield two data values(e.g., two bits with values of 0 and/or 1) from a row (e.g., row 519)and/or as stored in the sense amplifier and/or compute componentassociated with complementary digit lines 505-1 and 505-2. These datavalues could be input in parallel to each shared, differential I/O pair(e.g., shared I/O and shared I/O*) of the shared differential I/O line555.

While example embodiments including various combinations andconfigurations of sensing circuitry, sense amplifiers, computecomponent, dynamic latches, isolation devices, and/or shift circuitryhave been illustrated and described herein, embodiments of the presentdisclosure are not limited to those combinations explicitly recitedherein. Other combinations and configurations of the sensing circuitry,sense amplifiers, compute component, dynamic latches, isolation devices,and/or shift circuitry disclosed herein are expressly included withinthe scope of this disclosure.

Although specific embodiments have been illustrated and describedherein, those of ordinary skill in the art will appreciate that anarrangement calculated to achieve the same results can be substitutedfor the specific embodiments shown. This disclosure is intended to coveradaptations or variations of one or more embodiments of the presentdisclosure. It is to be understood that the above description has beenmade in an illustrative fashion, and not a restrictive one. Combinationof the above embodiments, and other embodiments not specificallydescribed herein will be apparent to those of skill in the art uponreviewing the above description. The scope of the one or moreembodiments of the present disclosure includes other applications inwhich the above structures and methods are used. Therefore, the scope ofone or more embodiments of the present disclosure should be determinedwith reference to the appended claims, along with the full range ofequivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are groupedtogether in a single embodiment for the purpose of streamlining thedisclosure. This method of disclosure is not to be interpreted asreflecting an intention that the disclosed embodiments of the presentdisclosure have to use more features than are expressly recited in eachclaim. Rather, as the following claims reflect, inventive subject matterlies in less than all features of a single disclosed embodiment. Thus,the following claims are hereby incorporated into the DetailedDescription, with each claim standing on its own as a separateembodiment.

1-20. (canceled)
 21. An apparatus, comprising: an array of memory cells;a cache coupled to the array; sensing circuitry comprising a pluralityof sense amplifiers each coupled to the array; and a shared input/output(I/O) line shared by each of the plurality of sense amplifiers; acommand interface coupled to the cache and configured to providecommands to the cache along with corresponding column addresses andupdated data received through the shared I/O line and to be written tothe cache; and tracking circuitry coupled to the cache, wherein thetracking circuitry is configured to track write addresses of datawritten to the cache from the shared I/O line.
 22. The apparatus ofclaim 21, further comprising a controller coupled to the cache andconfigured to: send a command for copying cache data from the cache tothe array, the command having an associated column address.
 23. Theapparatus of claim 22, wherein the controller is further configured totransfer data from the shared I/O line to the sensing circuitry andselectably transfer data from the plurality of sense amplifiers to aportion of the array corresponding to a number of columns of memorycells;
 24. The apparatus of claim 21, wherein the tracking circuitrycomprises latch circuitry and the column addresses are latched in thelatch circuitry.
 25. The apparatus of claim 24, wherein the trackingcircuitry is further configured to track each of the column addressesassociated with the updated data received to the cache via the commandinterface.
 26. The apparatus of claim 21, wherein the tracking circuitryis configured to set a flag associated with a first column address inresponse to updated data associated with the first column address beingwritten to the cache.
 27. The apparatus of claim 26, wherein thetracking circuitry further comprises a latch to store a data value thatindicates the flag is set.
 28. The apparatus of claim 26, wherein thetracking circuitry is configured to not set a flag associated with asecond column address in response to data associated with the secondcolumn address not being written to the cache.
 29. The apparatus ofclaim 21, wherein the tracking circuitry is configured to latch a datavalue that corresponds to a column address associated with at least oneof the write commands.
 30. A method, comprising: writing data stored inan array of memory cells to a cache; updating a portion of the datastored in the cache, wherein the updated data is transferred via ashared input/output (I/O) line coupled to each of a plurality of senseamplifiers coupled to the array and via a compute component coupled toat least one of the plurality of sense amplifiers; tracking columnaddresses associated with the updated portion of the data; and inresponse to receiving a write command, from a controller, to copy atleast the updated portion of data from the cache to the array, comparingthe column addresses associated with the write command with the trackedcolumn addresses.
 31. The method of claim 30, further comprising, inresponse to the column addresses matching the tracked column addresses,writing the updated portion of the data associated with each of thematched column addresses to the array.
 32. The method of claim 31,further comprising not writing portions of the data associated withcolumn addresses that do not match.
 33. The method of claim 30, furthercomprising, in response to a command being sent via a command interfaceto update a portion of the data associated with column addresses andstored in the cache with data received across the shared I/O line,modifying the portion of the data associated with the command.
 34. Anapparatus, comprising: an array of memory cells; sensing circuitrycomprising a plurality of sense amplifiers each coupled to the array;and a shared input/output (I/O) line shared by each of the plurality ofsense amplifiers; a controller coupled to a cache and configured totransfer data from the shared I/O line to the sensing circuitry andselectably transfer data from the plurality of sense amplifiers to aportion of the array corresponding to a number of columns of memorycells; a command interface coupled to the cache and configured toprovide commands to the cache along with corresponding column addressesand updated data received through the shared I/O line and to be writtento the cache; and tracking circuitry configured to compare the columnaddress of one of the commands for copying cache data from the cache tothe array to tracked addresses associated with the updated data receivedto the cache via the command interface.
 35. The apparatus of claim 34,wherein the controller is a DDR4 SDRAM controller.
 36. The apparatus ofclaim 34, wherein the controller is further configured to, in responseto the tracking circuitry matching the column address and one of thetracked addresses, write data associated with the each of the matchedcolumn addresses from the cache to the array.
 37. The apparatus of claim36, wherein the controller is further configured to not write dataassociated with a column address that does not match a tracked addressof the tracked addresses.
 38. The apparatus of claim 34, wherein thecommand interface is a DRAM command interface.
 39. The apparatus ofclaim 34, wherein the controller is further configured to cause latchingof a value in a latch in response to receiving a write commandassociated with a column address.
 40. The apparatus of claim 39, whereinthe controller is further configured to cause: writing data associatedwith the latched value to the array; and clearing of the latched valuein response to the writing of the data associated with the trackedcolumn addresses to the array.